A JFET can serve very different purposes depending on how it is connected. Place the output at the drain, and the device can provide voltage gain. Take the output from the source, and the same JFET can buffer a signal while presenting a lower impedance to the next stage. These two fundamental configurations—the common-source amplifier and the source follower—appear throughout low-noise preamplifiers, sensor interfaces, audio circuits, instrumentation and other precision analog systems. Understanding the differences between them helps engineers choose the right configuration, bias point and JFET for the job. WHAT DOES “COMMON” MEAN? The terms common-source and common-drain describe which JFET terminal is effectively common to both the input and output signal paths. In a common-source amplifier: The signal is applied to the gate. The output is taken from the drain. The source is the common reference point for the signal. In a source follower, also called a common-drain stage: The signal is applied to the gate. The output is taken from the source. The drain is effectively common to the input and output signal paths. The JFET may be the same, but changing the output terminal changes the circuit’s gain, phase relationship, output impedance and overall function. THE COMMON-SOURCE AMPLIFIER The common-source configuration is used primarily for voltage amplification. A small change in gate-to-source voltage changes the JFET’s drain current. That changing current develops a larger voltage variation across the drain resistor or active load, producing voltage gain at the drain. The output signal is inverted relative to the input. When the gate voltage moves in a direction that increases drain current, the voltage drop across the drain resistance increases and the drain voltage falls. The result is an output that is approximately 180 degrees out of phase with the input. Key characteristics of a common-source stage generally include: Voltage gain An inverted output High input impedance Moderate-to-high output impedance Greater sensitivity to device transconductance and drain loading Potential bandwidth reduction from the Miller effect The actual gain depends on the JFET’s transconductance, the drain resistance, the source resistance, the load and the device’s internal output resistance. A simplified gain relationship is: Av ≈ −gm × effective drain resistance The negative sign represents the phase inversion. This relationship is only an approximation. Source degeneration, loading, finite device output resistance and parasitic capacitances all influence the actual result. SOURCE DEGENERATION AND GAIN Many common-source amplifiers include a resistor between the source and ground. This source resistor introduces local negative feedback, often called source degeneration. As drain current increases, the voltage across the source resistor rises. This reduces the effective change in gate-to-source voltage and counteracts the original increase in current. Source degeneration can: Improve bias stability Improve linearity Reduce distortion Reduce sensitivity to device variation Lower voltage gain A bypass capacitor may be placed across the source resistor to reduce AC degeneration over a selected frequency range. This can increase AC gain while retaining the resistor’s DC bias stabilization. However, the capacitor value and the impedances surrounding it affect the amplifier’s low-frequency response. It should therefore be selected as part of the complete circuit design rather than treated as an ideal short circuit. THE SOURCE FOLLOWER A source follower takes its output from the JFET’s source terminal. As the gate voltage changes, the source voltage moves in the same direction. The source therefore “follows” the input signal. Unlike the common-source amplifier, the source follower does not normally provide voltage gain greater than one. Its voltage gain is typically slightly below unity. The source follower’s value comes from impedance transformation rather than voltage amplification. It presents a high impedance to the signal source while providing a lower output impedance to the following stage. This makes it useful for buffering high-impedance sensors, driving cables, isolating circuit stages and preventing a load from disturbing a sensitive signal source. Key characteristics of a source follower generally include: Voltage gain slightly below one A non-inverting output High input impedance Lower output impedance Local negative feedback Improved ability to drive the following stage The source follower does not create additional signal voltage. Instead, it helps preserve the voltage already present while making the signal more usable by the next circuit stage. WHY THE SOURCE FOLLOWER HAS LOWER OUTPUT IMPEDANCE The source follower contains strong local feedback. If the output voltage at the source is pulled away from the voltage established by the gate, the resulting change in gate-to-source voltage changes the JFET current in a direction that opposes the disturbance. This feedback reduces the effective output impedance. As a first-order approximation, the intrinsic output resistance contributed by the device is related to: Zout ≈ 1/gm The actual circuit output impedance also depends on the source resistor, load, bias arrangement and the JFET’s other small-signal parameters. A device with higher transconductance can generally provide a lower follower output impedance under comparable operating conditions. INPUT IMPEDANCE IS NOT DETERMINED BY THE JFET ALONE JFET gates draw extremely little current when the gate-channel junction is properly reverse biased. This allows both configurations to offer very high intrinsic input impedance. However, the input impedance of the finished circuit is not determined by the JFET alone. It may also be limited by: Gate-bias resistors Protection components Leakage across the circuit board Input capacitance Connector or cable leakage Contamination and moisture Sensor impedance Frequency A JFET with picoampere-level gate leakage cannot deliver picoampere-level system performance if the surrounding board, bias network or protection circuitry introduces substantially greater leakage. The complete input path must be evaluated. THE MILLER EFFECT IN A COMMON-SOURCE STAGE The capacitance between the gate and drain can have a much greater effect in an inverting common-source amplifier than its datasheet value might initially suggest. Because the drain signal moves in the opposite direction from the gate signal, the voltage across the gate-to-drain capacitance changes by more than the input voltage alone. From the input’s perspective, this can make the capacitance appear multiplied by the stage gain. This phenomenon is known as the Miller effect. The increased effective input capacitance can interact with a high source impedance to reduce bandwidth, slow signal transitions and affect stability. The Miller effect becomes especially important when: The common-source stage has high voltage gain The signal source has high impedance The application requires wide bandwidth The JFET has significant gate-to-drain capacitance Several stages are cascaded A device with lower capacitance may therefore provide better high-frequency performance even if another device has a lower headline noise specification. CAPACITANCE IN A SOURCE FOLLOWER A source follower behaves differently because the source moves in the same direction as the gate. Since the gate and source voltages change together, the AC voltage developed across the gate-to-source capacitance can be reduced. This bootstrapping effect can lower the apparent influence of that capacitance at the input. This is one reason source followers are useful in high-impedance and capacitance-sensitive applications. The effect is not perfect. The follower’s gain is below one, and the circuit still includes gate-to-drain capacitance, stray capacitance, board capacitance and the input capacitance of the following stage. Nevertheless, a properly designed source follower can isolate a sensitive, high-impedance source from a more demanding load. HEADROOM AND SIGNAL SWING Neither configuration can be evaluated by gain and impedance alone. The JFET must be biased so that it remains in its intended operating region throughout the required signal swing. In a common-source amplifier, the drain voltage must have enough room to move upward and downward without driving the device into cutoff or an unsuitable low-voltage operating region. In a source follower, the source sits at a voltage determined by the gate voltage, gate-to-source voltage and bias current. The output cannot simply follow the input to either supply rail. Designers should consider: Supply voltage Drain current Drain-to-source voltage Gate-to-source voltage Expected input amplitude Required output swing Load current Device IDSS range Temperature variation A source follower may offer excellent buffering while still clipping if its bias point or available headroom is inadequate. COMMON-SOURCE VS. SOURCE FOLLOWER Common-Source Primary function: Voltage amplification Voltage gain: Often greater than one Output phase: Inverted Input impedance: High, but influenced by the bias network and capacitance Output impedance: Generally higher than a source follower Bandwidth consideration: Miller multiplication of gate-to-drain capacitance Typical uses: Preamplifiers, gain stages and signal conditioning Source Follower Primary function: Buffering and impedance transformation Voltage gain: Slightly below one Output phase: Non-inverting Input impedance: High, but influenced by the bias network and capacitance Output impedance: Lower than a common-source stage Bandwidth consideration: Reduced effect of gate-to-source capacitance through bootstrapping Typical uses: Sensor buffers, cable drivers, stage isolation and impedance matching WHICH CONFIGURATION SHOULD YOU USE? Use a common-source stage when the circuit needs: Voltage gain Amplification of a small sensor signal An inverting stage A discrete low-noise voltage amplifier Signal conditioning before a later stage Use a source follower when the circuit needs: High input impedance Lower output impedance Isolation between stages Reduced loading of a sensor or signal source Improved drive for a cable, capacitor or following amplifier Near-unity voltage transfer without phase inversion Many practical circuits use both. A common-source stage may provide the required voltage gain, followed by a source follower that prevents the load from reducing that gain or degrading the signal. SELECTING A JFET FOR EACH CONFIGURATION The best JFET depends on the circuit and application. Important parameters may include: Voltage-noise density Current noise and gate leakage Transconductance Input capacitance Gate-to-drain capacitance IDSS range VGS(off) Drain-to-source voltage rating Matching and thermal tracking Package and board layout Production testing and guaranteed limits For a common-source amplifier, transconductance, noise and gate-to-drain capacitance can be especially important because they directly affect gain and bandwidth. For a source follower, transconductance influences output impedance and drive capability, while capacitance and leakage remain important when buffering a high-impedance source. No single parameter identifies the best device. Noise, capacitance, bias current, available headroom and source impedance must be considered together. LINEAR SYSTEMS JFET OPTIONS Linear Systems offers several JFETs that can be evaluated for common-source and source-follower designs. LSK170 The LSK170 is a low-noise, single N-channel JFET suited for low-level amplification and buffering in audio, instrumentation and sensor applications. LSK389 The LSK389 is a monolithic dual N-channel JFET designed for applications requiring low noise, close matching and thermal tracking. It is well suited for differential input stages and other precision circuits in which the relationship between two devices matters. LSK489 The LSK489 is a lower-capacitance monolithic dual N-channel JFET. Its combination of matching, noise performance and reduced capacitance can benefit higher-speed or capacitance-sensitive front ends. LSK189 The LSK189 is a low-capacitance N-channel JFET that can be useful in high-impedance sensor interfaces and source-follower applications where input capacitance is a major consideration. The appropriate device and IDSS grade should be selected using the current datasheet and the circuit’s required bias current, noise, capacitance, voltage and signal-swing conditions. COMMON MISCONCEPTIONS “A source follower has no gain.” A source follower normally has no voltage gain greater than one, but it can provide current and power gain while transforming impedance. That can be more valuable than voltage gain in many applications. “A common-source amplifier always has high gain.” Its gain depends on transconductance, drain resistance, source degeneration, loading and operating point. A heavily loaded or strongly degenerated stage may have modest gain. “A JFET automatically gives the circuit extremely high input impedance.” The gate itself may have extremely high resistance, but the circuit’s bias network, contamination, leakage and capacitance determine the input impedance engineers actually obtain. “The lowest-noise JFET is always the best choice.” The circuit may also require low capacitance, a particular IDSS range, sufficient transconductance, matching, voltage capability or a specific package. The best device is the one whose complete set of characteristics fits the application. CONNECTING THE LEARNING SERIES TO PRACTICAL DESIGN The Linear Systems Learning Series explains the device principles behind precision analog design: how JFET parameters behave, why test conditions matter and how circuit configuration changes device performance. Our weekly JFET Design Spotlight complements that foundation by examining practical circuits and design approaches. Together, the two series connect datasheet specifications and device physics to the decisions engineers make at the schematic and bench. The Learning Series explains the “why.” The JFET Design Spotlight shows the “how.” ENGINEERING TAKEAWAY The same JFET can perform two very different jobs. A common-source stage uses the JFET’s transconductance to produce voltage gain, with an output that is inverted relative to the input. A source follower trades voltage gain for high input impedance, lower output impedance and improved isolation between circuit stages. The correct choice depends on what the signal needs next: amplification or buffering. Understanding that distinction helps engineers make better decisions about biasing, impedance, bandwidth, noise, capacitance and device selection. Would you like to sample Linear Systems’ low-noise JFETs and precision discrete semiconductors: #JFET #AnalogDesign #LowNoiseDesign #ElectronicsEngineering #SourceFollower #CommonSource #SignalIntegrity #Semiconductors #LinearSystems #LearningSeries

What happens when passionate audio enthusiasts, talented engineers, and creative builders come together? Some truly fascinating conversations! Linear Systems' Paul Norton attended Burning Amp 2026, connecting with members of the DIY audio community to learn about their projects, innovative designs, and passion for high-performance sound. From custom speaker systems and amplifiers to inventive audio electronics, these conversations highlight the creativity, technical expertise, and hands-on experimentation that make this community so special. 🎥 We're excited to share our Burning Amp 2026 Interview Series! Hear directly from the builders and innovators as they discuss their creations and share what inspires their work. ▶️ Watch the full interview series on YouTube: https://www.youtube.com/playlist?list=PLYbUmb9i8PVM A big thank-you to everyone who took the time to share their projects and insights with us! At Linear Systems, we're proud to support the engineers and innovators who continue to push the boundaries of analog and audio technology. #BurningAmp2026 #DIYAudio #AudioEngineering #Audiophile #AnalogElectronics #LinearSystems

Sometimes the most effective analog solutions are also the simplest. This design demonstrates how a low-noise, high-gain differential amplifier can deliver excellent linearity, wide bandwidth, and fast transient response without feedback. “The sensing and manipulation of differential signals can take on a myriad of configurations using all types of semiconductor types and vacuum tubes. Inputs have all ranges of impedances, all ranges of source loading conditions, and what becomes of that signal: current gain, voltage gain, bandwidth, reflected circuit dynamics, differential or single-ended through conversion, group delay, feedback phase error over frequency, or any other quandary needing definition. For this case, there was a defined task requiring utmost simplicity, high performance, and a wide range of voltage operation to gain up a small low-Z guitar pickup. For this low an impedance, a differential emitter input was chosen, being in the range of the pickup’s impedance character and its limited voltage output of <15 mV. The differential input impedance of this bipolar emitter pair is 25 mV / 185 µA × 2 = 270 Ω, or a damping coefficient of about 3:1 relative to the pickup impedance including the shunt resistor. A high-Q coil will ring if not properly terminated and results in unwanted odd voicing. Small signals have an advantage in amplification where high gain can be linear without feedback as long as the signal is less than the square law voltage effects of the differential junctions. Linear operation is less than 14 mV differential input for silicon bipolar transistors operating either common emitter or common base. Because of the low-Z input, a grounded base, differential emitter is used. As is typical, using an LS352 PNP mirror to ratio the differential LS312 NPN pair currents into a single-ended output works well and could be increased to 60 dB of gain if a larger operating current were tolerable. Here, the circuit draws less than 0.5 mA and has an output impedance of about 25 kΩ. Circuit gain is 42 dB operating from a 9 V battery. Being a non-feedback gain circuit, frequency response is flat up to 200 kHz, has low harmonic content and acute transient response without overshoot or ringing. Though designed for a specialized bass guitar pickup, this approach is easily seen as a drop-in for other instrumentation applications. The step response is shown with square wave 300 ns rise and fall times ±10 mV input. As usual …… Kirkwood Rough” Figure 1: Mag Pickup WF Figure 2: Mag Pickup Frequency Figure 3: Mag Pickup Transient Precision analog performance starts with the right components. Linear Systems' low-noise JFETs and precision bipolar transistors provide engineers with proven building blocks for audio, instrumentation, sensor interfaces, and other demanding analog applications. Explore our semiconductor solutions and request free evaluation samples: #LinearSystems #JFETDesignSpotlight #AnalogDesign #LS312 #LS352 #BipolarTransistors #LowNoise #PrecisionAnalog #AudioEngineering #BassGuitar #CircuitDesign #DiscreteSemiconductors #AnalogElectronics #Instrumentation #ElectronicsEngineering

When engineers evaluate a JFET, specifications such as noise, transconductance, input capacitance, and IDSS often receive most of the attention. But in high-impedance circuits, another specification can become extremely important: gate leakage current. JFET gate current may be extraordinarily small, often measured in picoamps or nanoamps. But when that tiny current interacts with a very high source impedance, it can create a measurable error. Understanding gate leakage, and the conditions under which it is specified, is therefore important when selecting a JFET for precision analog applications. What Is Gate Leakage? A JFET gate forms a PN junction with the channel. During normal JFET operation, this junction is reverse biased, so only a very small reverse current flows. Datasheets commonly specify this as IGSS, or gate-to-source reverse current. This extremely low gate current is one of the characteristics that makes JFETs particularly useful in circuits requiring very high input impedance. But “very small” does not always mean insignificant. Why Picoamps Can Matter The impact of leakage current depends heavily on the impedance of the circuit. A useful way to visualize this is: VERROR = ILEAK × RSOURCE For example: 1 pA × 1 GΩ = 1 mV Just one picoamp of leakage current interacting with a 1 GΩ source impedance can therefore correspond to a 1 mV voltage error. In a low-impedance circuit, that same current might be essentially irrelevant. In an extremely high-impedance sensor interface, however, it can become an important part of the error budget. That is why gate leakage should always be considered in the context of the actual source impedance and required measurement accuracy. Where Gate Leakage Matters Most Very low gate current becomes particularly valuable in applications involving high source impedances or extremely small signals. Examples include: Piezoelectric sensors — These sensors can present very high source impedances, making low input current particularly important. Photodiode amplifiers — Small detector currents can make leakage currents an important consideration in precision front-end design. Charge amplifiers — Maintaining extremely low input current helps preserve measurements involving very small quantities of charge. Electrometers — These instruments are specifically designed to measure extremely small currents, voltages, and charges. Radiation detectors — Detector front ends may need to process extremely small signals while introducing minimal additional current. Scientific instrumentation — Precision measurement systems frequently combine small signals with high source impedances, making leakage an important design consideration. Temperature Matters Gate leakage should never be evaluated without considering the conditions under which it was measured. Because the JFET gate-channel interface is a semiconductor PN junction, gate leakage can increase as temperature rises. This is why engineers should look beyond a single IGSS number on a datasheet and pay attention to the specified test conditions, including: VGS, VDS, junction or ambient temperature, and whether the specification is typical or maximum. A device that performs extremely well under room-temperature test conditions may behave differently at elevated operating temperatures. For precision designs, the relevant question isn't simply: “What is the gate leakage?” It is: “What is the maximum gate leakage under the conditions my circuit will actually experience?” The JFET Isn't the Only Source of Leakage At picoamp-level currents, the semiconductor itself may not be the only concern. Leakage can also be introduced elsewhere in the signal path through factors such as PCB contamination, moisture, flux residue, connectors, sockets, cable insulation, board materials, and other components connected to the input node. In extremely high-impedance designs, techniques such as careful PCB cleaning, guarding, appropriate insulating materials, and thoughtful board layout may become just as important as selecting a low-leakage JFET. The entire input path has to be considered as a system. Gate Leakage and Noise Are Not the Same Thing It's also important not to confuse low gate leakage with low noise. A JFET can have extremely low gate current without necessarily being the optimum device for every low-noise application. Depending on the circuit, engineers may need to balance several characteristics: Voltage noise Current noise Gate leakage Input capacitance Transconductance Source impedance Bandwidth Operating current The best device is the one whose characteristics match the requirements of the entire circuit. What to Look for on a JFET Datasheet When gate leakage is important to your design, don't stop at the headline specification. Look for: IGSS — Gate-to-Source Reverse Current Maximum versus typical specifications Voltage conditions used for the measurement Temperature at which IGSS is specified Input capacitance Noise specifications Other operating conditions associated with the specification These details provide a much better indication of how the device may behave in the actual application. The Takeaway Gate leakage may be measured in picoamps, but in a high-impedance circuit, those picoamps can matter. The higher the source impedance and the smaller the signal, the more important it becomes to evaluate IGSS, temperature, operating conditions, and the entire input path. Understanding these relationships helps engineers choose the right JFET and avoid errors that might otherwise be overlooked. Designing a High-Impedance Analog Front End? Linear Systems offers precision JFETs and other discrete semiconductor solutions for demanding low-noise and high-impedance analog applications. Explore our JFET portfolio or contact us for FREE engineering samples. Designed for Precision. Built for Performance.Quality Through Innovation Since 1987. www.linearsystems.com #LinearSystems #LearningSeries #JFET #GateLeakage #IGSS #AnalogDesign #PrecisionAnalog #HighImpedance #LowNoise #Semiconductors #ElectronicsEngineering

Most discussions about JFETs focus on N-channel devices. That makes sense. N-channel JFETs are widely used in low-noise amplifiers, sensor interfaces, instrumentation inputs and professional audio equipment. But N-channel devices represent only one side of what is possible. When N-channel and P-channel JFETs are used together, designers can build complementary circuit stages that handle signals more symmetrically, simplify biasing, improve drive capability and enable architectures that would be difficult to implement with only one polarity. Understanding complementary JFETs—and recognizing that “complementary” does not mean “electrically identical”—can open additional possibilities in precision analog design. WHAT DOES “COMPLEMENTARY” MEAN? N-channel and P-channel JFETs operate with opposite voltage and current polarities. For an N-channel JFET: The device conducts when VGS = 0 Making the gate more negative relative to the source reduces drain current The device is commonly used with a positive drain-to-source voltage For a P-channel JFET, the operating polarities are reversed: The device also conducts when VGS = 0 Making the gate more positive relative to the source reduces the magnitude of the drain current The device is commonly used with the opposite drain-to-source polarity A complementary circuit uses both device types so that each performs a related function on an opposite side of the signal or supply structure. This is similar in concept to complementary NPN and PNP bipolar transistors or N-channel and P-channel MOSFETs. However, JFETs bring their own combination of high input impedance, low noise, low gate-current requirements and analog linearity. WHY USE BOTH POLARITIES? Many useful circuits can be built entirely with N-channel JFETs. However, access to an appropriate P-channel complement gives the designer additional architectural options. Complementary JFETs can be used to: Construct push-pull source followers Build fully complementary differential input stages Source and sink signal current Simplify direct-coupled circuit designs Create positive- and negative-polarity current sources Develop low-distortion buffers and preamplifiers Reduce dependence on level-shifting networks Preserve high input impedance in both halves of a circuit The benefit is not simply having another device available. It is having the freedom to approach the circuit from both supply directions. COMPLEMENTARY SOURCE FOLLOWERS A source follower is commonly used as a buffer because it provides high input impedance and lower output impedance without adding substantial voltage gain. A single-JFET source follower can work very well when the required output-current direction and signal range are limited. A complementary source follower adds a device of the opposite polarity so that one device can source current while the other sinks it. Depending on the circuit and bias arrangement, a complementary follower may provide: More symmetrical output-current capability Lower output impedance Improved drive into the following stage Greater usable signal swing Reduced reliance on a large passive load resistor However, the transition between the two devices must be carefully controlled. Poor biasing can introduce crossover effects, offset or unequal operation between the positive and negative portions of the waveform. The topology creates the opportunity for improved performance, but device selection and bias design determine whether that opportunity is realized. FULLY COMPLEMENTARY INPUT STAGES Complementary JFETs can also be used in the input stage of a precision amplifier. A fully complementary input structure may combine an N-channel differential pair with a P-channel differential pair. Depending on the circuit, this can provide more balanced operation around the supply rails, improve positive- and negative-going signal behavior or simplify direct coupling between stages. This type of architecture can be useful in: Audio preamplifiers Phono stages Instrumentation amplifiers Sensor interfaces Discrete operational amplifiers High-speed comparators Test and measurement equipment Monolithic dual JFETs are particularly valuable in differential stages because the two transistors within each device are fabricated on the same die. This improves matching and thermal tracking within the N-channel pair and within the P-channel pair. Better matching can help reduce input offset, improve common-mode rejection and provide more consistent behavior as temperature changes. COMPLEMENTARY DOES NOT MEAN IDENTICAL This is one of the most important points for designers to understand. A P-channel JFET described as the complement of an N-channel JFET should not automatically be treated as a perfect mirror image. The devices may have similar intended operating characteristics, but differences can remain in: IDSS VGS(off) Transconductance Input capacitance Reverse transfer capacitance Voltage-noise density Gate leakage Breakdown voltage Temperature behavior Response to changes in VDS Even devices with closely aligned headline specifications may behave differently when operated at another drain current, drain-to-source voltage or temperature. For that reason, complementary devices should be evaluated at the circuit’s actual operating point—not only at the datasheet’s headline test condition. WHAT SHOULD ENGINEERS COMPARE? When choosing complementary JFETs, engineers should consider more than polarity and package style. Important questions include: Do the IDSS ranges overlap appropriately? How do the VGS(off) ranges compare? What transconductance does each device provide at the intended drain current? Are the capacitances appropriate for the required bandwidth? How does voltage noise compare at the frequencies that matter? What gate leakage can be expected at the operating voltage and temperature? Are the devices being used as individual transistors or as monolithic differential pairs? Will the devices behave as required across the complete supply-voltage and temperature range? Does the circuit require additional selection or matching under application-specific conditions? A complementary pair selected only by part-family reputation may not provide the expected symmetry. The devices must be evaluated as part of the complete circuit. SINGLE DEVICES VERSUS MONOLITHIC DUALS Linear Systems offers complementary options in both single and monolithic-dual configurations. The LSK170 and LSJ74 families provide complementary N-channel and P-channel single JFETs. These devices are useful in source followers, output stages, current sources, audio circuits and other designs where individual transistor placement provides the required flexibility. The LSK489 and LSJ689 provide complementary N-channel and P-channel monolithic dual JFETs. Within each dual device, both transistors are fabricated on the same die. This provides closer electrical matching and thermal tracking than designers would normally obtain by selecting two unrelated discrete devices. The LSK489 and LSJ689 are designed for applications requiring a combination of: Low voltage noise Low input capacitance High input impedance Tight matching within each dual Low offset and temperature drift Compact surface-mount package options Because the N-channel and P-channel pairs remain separate devices, the designer must still compare their cross-polarity behavior under the intended circuit conditions. WHERE COMPLEMENTARY JFETS ARE ESPECIALLY USEFUL Complementary JFETs can be valuable anywhere a small signal must be handled with high input impedance, low added noise and balanced positive- and negative-going performance. Examples include: Microphone and phono preamplifiers High-impedance sensor interfaces Piezoelectric and acoustic instrumentation Discrete operational amplifiers Low-distortion audio buffers Sample-and-hold circuits Voltage-controlled resistors Precision current sources Wideband differential amplifiers Scientific and medical instrumentation They are particularly attractive when the designer wants a fully discrete signal path without giving up the benefits normally associated with precision input devices. ENGINEERING TAKEAWAY Complementary JFETs give analog designers something increasingly valuable: flexibility. An N-channel device may provide excellent performance on its own. Adding an appropriate P-channel complement makes it possible to build more symmetrical buffers, differential stages, current sources and direct-coupled amplifier architectures. But complementary devices should never be assumed to be perfect electrical mirror images. Engineers must still evaluate: Bias current VGS(off) and IDSS ranges Transconductance Noise Capacitance Leakage Temperature behavior Performance at the actual operating point The best complementary design is not created simply by placing an N-channel and P-channel JFET beside each other. It comes from understanding how the two devices behave together. Would you like to try Linear Systems’ complementary JFET solutions free of charge?

A JFET datasheet may list an impressively low voltage-noise number—but how was that number measured, at what frequency, and does it represent a typical value or a guaranteed maximum? Those details matter. At nanovolt-per-root-hertz levels, the measurement system, test conditions and specification method can significantly influence the result. Understanding what sits behind the published number helps engineers make more meaningful comparisons between devices. WHAT DOES A JFET NOISE SPECIFICATION MEAN? JFET voltage noise is commonly expressed as a noise-voltage density: nV/√Hz This value describes the noise generated by the device over a one-hertz bandwidth at a specified frequency and operating condition. A lower number generally indicates that the device contributes less voltage noise to the signal chain. However, the number should never be evaluated by itself. Engineers should also consider: The frequency at which the measurement was taken The device’s drain current and drain-to-source voltage The source impedance presented to the gate, including its resistive and capacitive components Whether the value is typical or guaranteed The measurement bandwidth The test circuit and fixture gain Whether compliance is verified through characterization, sampling or individual-device testing Without this context, two similar-looking noise specifications may not provide the same level of assurance. WHY FREQUENCY MATTERS JFET noise is not constant across all frequencies. At lower frequencies, 1/f noise—also known as flicker noise—typically becomes more significant. At higher frequencies, the device generally reaches a flatter broadband-noise region. This is why a single noise value at one frequency does not describe the device’s complete noise performance. For example, measuring at multiple frequencies such as 10 Hz, 100 Hz, 1 kHz and 10 kHz provides a more useful view of how the device transitions from its low-frequency 1/f region into its broadband-noise region. The frequency must therefore be included whenever noise performance is compared. WHY SOURCE IMPEDANCE MATTERS Source impedance is another essential condition when evaluating JFET noise. When a JFET’s intrinsic voltage noise is measured, the gate is typically connected through a defined—and often very low—source impedance. This minimizes the voltage developed by input-current noise and helps isolate the device’s voltage-noise contribution. In an actual circuit, however, total input-referred noise also includes the thermal noise of the source resistance and the voltage produced when the JFET’s input-current noise flows through the source impedance. For a primarily resistive source, the total input-referred noise can be approximated as: e_total = √[e_n² + (i_nR_s)² + 4kTR_s] where: e_n is the JFET’s input voltage-noise density i_n is its input current-noise density R_s is the source resistance k is Boltzmann’s constant T is absolute temperature Source impedance may also include capacitance and can therefore change with frequency. This is especially important with piezoelectric sensors, photodiodes, microphones and other high-impedance or capacitive sources. A voltage-noise number should therefore be interpreted together with its source impedance, bias conditions, frequency and measurement bandwidth. TYPICAL VALUES VERSUS MAXIMUM LIMITS One of the most important distinctions on a datasheet is whether a noise value is listed as typical or maximum. A typical value represents expected or representative performance based on characterization data. It does not necessarily guarantee that every production device will meet that exact value. A maximum specification establishes a defined upper limit under the stated test conditions. This provides a clearer design boundary for engineers who need predictable performance. The distinction becomes especially important when comparing replacement devices. For example, a device with maximum noise limits should not be evaluated as though its specification were equivalent to a competitor’s typical value measured at only one frequency. The headline numbers may appear similar, while the level of assurance behind them may be very different. WHY LOW-NOISE MEASUREMENT IS DIFFICULT Measuring JFET noise near the nanovolt-per-root-hertz level is not as simple as connecting the device to a spectrum analyzer. The test setup can introduce noise and measurement errors of its own. Important considerations include: Shielding from electromagnetic interference Grounding and cable placement Noise from the power supplies The voltage noise and current noise of the first amplifier stage The source impedance and capacitance presented to the JFET gate Fixture gain and analyzer sensitivity Measurement bandwidth and FFT settings The number of measurements averaged Input capacitance and the Miller effect The drain current used during testing Sufficient settling time before the measurement begins If these factors are not controlled, the test system may measure itself as much as it measures the JFET. VERIFYING THE MEASUREMENT SYSTEM Before testing a low-noise device, the measurement system must be checked against a known reference. Linear Systems uses a noise-reference adapter to verify that the test fixture and analyzer produce the expected readings before device measurements are performed. The system is checked at multiple frequencies so that problems with the fixture, connections, gain or analyzer can be identified before production testing begins. This step is critical. A test result is only credible if the measurement system has first demonstrated that it can accurately detect the expected noise level. A known resistance may also be used as a calibration reference because its thermal-noise density can be calculated from: e_n = √(4kTR) where: k is Boltzmann’s constant T is absolute temperature R is resistance Comparing the calculated thermal-noise value with the measured result can help confirm the performance of the test chain. SHIELDING, SETTLING AND AVERAGING At these signal levels, ordinary environmental interference can overwhelm the device noise being measured. A shielded fixture helps isolate the device under test from power-line interference, radio-frequency signals and other electrical activity in the surrounding environment. The device must also be allowed to settle at the required voltage and current before its noise is measured. Taking a reading too early can produce a result that does not represent stable operation. Averaging multiple measurements helps reduce random variation in the displayed spectrum. However, averaging cannot correct a poor grounding arrangement, insufficient shielding or an improperly configured front end. The physical test environment remains essential. THE IMPORTANCE OF THE OPERATING POINT JFET noise performance depends partly on the device’s operating point. Drain current affects transconductance, voltage noise and other device characteristics. A noise specification is therefore meaningful only when the corresponding bias conditions are provided. IDSS selection can also influence how consistently devices operate within a circuit. A tighter IDSS range may simplify biasing and reduce unit-to-unit variation. A wider range may provide a more economical device option but require the circuit to accommodate greater variation. Additional electrical selections can provide tighter performance when an application requires it, but they also add testing, handling and production cost. DIFFERENT LEVELS OF NOISE ASSURANCE Not every JFET is tested in the same way, and not every Linear Systems JFET is 100% noise tested. Depending on the product and its specifications, noise performance may be supported through: Device characterization Guaranteed datasheet limits Production-lot sampling Individual-device testing Additional customer-requested selections Selected Linear Systems JFETs are individually tested for voltage noise when required by the product specification and production process. For example, the LSK389 and the LSK170C in the SOT-23 package receive 100% voltage-noise testing. Other products may use different testing or selection strategies based on their specifications, applications and market requirements. Individual testing offers a higher level of verification, but it also requires specialized equipment, additional production time and careful handling. It may therefore be applied selectively where the device specification and intended use justify it. WHAT ENGINEERS SHOULD LOOK FOR When comparing low-noise JFETs, engineers should ask: Is the noise value typical or guaranteed? At what frequency was it measured? What were the drain current and drain-to-source voltage? What source impedance was presented to the gate, and does it represent the intended application? Does the datasheet show low-frequency and broadband performance? Is the specification based on characterization, sampling or individual testing? What bandwidth and test method were used? Does the circuit require a particular IDSS range or additional selection? Are input capacitance, transconductance and noise being evaluated together? The device with the lowest headline number is not automatically the best choice. The most appropriate device is the one whose complete electrical characteristics, test conditions and level of assurance fit the application. LINEAR SYSTEMS LOW-NOISE JFETS Linear Systems offers a range of low-noise JFETs for sensor interfaces, instrumentation, professional audio, test and measurement equipment, medical electronics and other precision applications. The product family includes: LSK170 single N-channel JFET LSK389 monolithic dual N-channel JFET LSK489 lower-capacitance monolithic dual N-channel JFET LSJ74 single P-channel JFET LSJ689 monolithic dual P-channel JFET LSBF862 N-channel JFET and BF862 replacement Each device should be evaluated using its current datasheet, complete test conditions and applicable production-testing requirements. ENGINEERING TAKEAWAY A low-noise specification is only as meaningful as the conditions and verification behind it. Engineers should look beyond the headline nV/√Hz number and consider: Frequency Bias conditions Source impedance and source capacitance Bandwidth Typical versus maximum limits Measurement methodology Production-testing coverage Understanding these details leads to better device comparisons, more predictable circuit performance and fewer surprises in low-noise signal-chain design. Would you like free samples or more information? #JFET #LowNoiseDesign #AnalogDesign #SemiconductorTesting #ElectronicsEngineering #SignalIntegrity #LinearSystems #LearningSeries

JFETs are commonly used in amplifiers, current sources, variable resistors, and oscillators, but sometimes the most interesting designs come from using them in ways you wouldn’t normally expect. This week’s Design Spotlight explores one of those “odd uses”: creating a negative resistance effect with complementary N-channel and P-channel JFETs. “Use of JFETs in typical applications range from amplifiers to variable resistors and oscillators, among many other applications, but then there are some odd uses to consider. 1902 was the year that a high-powered dynamic method of exciting a resonant circuit for continuous Radio Frequency generation was proposed by Valdemar Poulsen. It consisted of a circuit with a Carbon/copper poled arc within a Hydrogen or Methane gas environment cross to an electromagnetic field in a series connection. This created a critically managed Negative resistance that could resonate an L/C tank continuously. Noted in Moorcroft Principles of Radio 1921, some crystal diodes at the time exhibited negative resistance but were deemed unreliable for any practical use. Long later, an electron tunneling diode effect was invented by Leo Esaki in 1957, having useful negative resistance properties for high frequency use. Negative resistance happens when an increase in current through a two-terminal device results in decreased voltage, which brings us to a curious Negative resistance effect that can be made with N and P channel JFETs. JFETs are known to be normally on and proceed to cutoff with a channel depletion voltage applied to the gate. If one were to place a P-channel and N-channel JFET part in series, drains common, and connect the gates to each other’s source voltage polarities, channel conductance starts at 0 volts and increases with applied voltage. At some point, however, conductance with increasing voltage will peak and begin to decrease thereafter as the gates deplete both JFET channels. The combined cutoff voltage of both FETs with continuing applied voltage reduces channel conductance to zero. This negative resistance slope can then be used as an active gain function for the purpose of generating oscillations with a two-terminal connection or even as an amplifier for voltage. This JFET pair has a Negative resistance midpoint of ~4 volts and is ~2Kohms in use as an active gain element. Not that there is a great use for such a circuit, so it’s simply presented here as the oddity that it is to think about. A practical use: I have a couple of these on the bench to just randomly test L-Cs for resonant frequency. Conveniently, the NJ and PJ pair does not reverse to a positive conductance after the negative slope ends, like a Tunnel Diode does, as shown in the DC sweep. Fig 1) DC V/I profile for the example JFETs Fig 2) Negative resistance amplifier Fig 3) Neg Res Amplifier Frequency response Fig 4) Negative resistance oscillator DC V/I profile for the example JFETs Negative resistance amplifier Neg Res Amplifier Frequency response Negative resistance oscillator As Usual …. Kirkwood Rough” Sometimes an unusual device characteristic opens the door to an entirely different circuit approach. Linear Systems offers a broad range of N-channel and P-channel JFETs for precision analog applications and design experimentation. Interested in evaluating a device for your next design? Contact us for FREE engineering samples. #LinearSystems #JFET #DesignSpotlight #NegativeResistance #AnalogDesign #CircuitDesign #Oscillator #AnalogElectronics #Semiconductors #ElectronicsEngineering

More design flexibility. Less board space. Linear Systems has expanded the SD5400 quad analog switch family with a new compact 3 × 3 mm QFN-16 package—giving designers another surface-mount option for space-constrained, high-speed analog applications. The SD5400 integrates four independent, bidirectional SPST switches on a common substrate. Built using our proprietary lateral DMOS process, it combines low on-resistance, low interelectrode capacitance and exceptionally fast switching performance. Key features include: • Four independent, bidirectional SPST switches • ±10 V analog signal capability • Typical turn-on time of just 1 ns • Reverse transfer capacitance as low as 0.2 pF • Integrated Zener gate protection • Compact 3 × 3 mm QFN-16 package The new QFN-16 option makes it easier to incorporate the SD5400 into designs where board space, high-density surface-mount assembly and fast analog switching are critical. View the SD5000/SD5400 Series datasheet below for complete electrical specifications, the QFN-16 pin configuration, package dimensions and ordering information. Contact Linear Systems for samples, pricing or technical support. #LinearSystems #AnalogSwitch #DMOS #QFN #AnalogDesign #Semiconductors

This week’s Design Spotlight is another great example of how JFETs and precision discrete components can come together to solve demanding analog design challenges. “Though there was another Piezo sensor earlier, this one has a bit more gain and a design bandwidth of 1.3 MHz. This circuit uses, as you’d expect, a low noise LSK389 differential JFET pair cascoded by Q1 & Q2 into a Widlar style current mirror. The LS310 transistor pair maintains constant voltage, low impedance terminations for the differential FETs where gate to drain potential is constant with respect to the signal input. Q1 and Q2 also eliminate the miller effect improving bandwidth in cascode. An LT1055 OpAmp provides little parasitic high frequency load as a transimpedance amp for the mirror output. A Linear Systems J502 current source diode serves to bias gate and base voltages of the lower two sections through Zener diodes. Another J502 diode supplies a high Z source current for the differential front end. Degeneration resistors are used in the LSK389 sources to linearize input voltage range 10% higher than with a direct source connection. The J500 series fixed current source diodes often find their way into a wide range of circuits from floating voltage resistive drops to most High Z source requirements. Fig 1 shows a -3db response from 100KHz to 1.3MHz by varying Cc from 33pF to 3.3pF. Overall salient design points are : High Z Differential JFET input, Cascoded low Z FET drain isolation, Widlar style current mirror, Transimpedance translator of current to voltage output ……. Not much to it….. But very effective. As Usual ……. Kirkwood Rough” Designing your own high-performance analog front end? Linear Systems offers the LSK389 matched dual JFET, LS310 matched transistor pair, J500 Series Current Regulating Diodes, and a broad range of precision discrete semiconductors for demanding analog applications. Interested in FREE engineering samples? Contact us to discuss your application and the devices you'd like to evaluate. #LinearSystems #JFET #DesignSpotlight #LSK389 #LS310 #J500 #AnalogDesign #PiezoSensor #LowNoise #PrecisionAnalog #AnalogElectronics #Semiconductors

What happens when you rethink low-noise amplifier design from a clean sheet? This design explores paralleling LSK389 JFETs to push noise even lower. “Things happen while throwing out historical habits in favor of a clean piece of paper. Differential Amplifiers, being relatively commonplace in analog circuit design, have traditionally followed familiar circuit practices regarding noise. For this discussion JFETs are of interest though Bipolar parts similarly apply. Front end noise is the algebraic sum between the first stage JFETs and if on a common Die like a dual, have some advantage of common mode noise reduction if they’re differentially sensed. Common mode noise on interleaved Dies like the LSK389 dual is significantly lower than individual matched Dies due to matched proximity doping uniformity. Another technique of front-end noise reduction is to parallel gain elements together where the noise is reduced by the root of the number of paralleled devices. Noise= 1/√N × (single device noise) where N= number of devices in parallel. However, paralleling has its tradeoffs of higher IDS, increased Vgs and higher input capacitance, but, if high impedance and low noise is a goal, that’s it. Effectively, bigger Dies = lower noise along with the tendency of noise being inversely proportional to device Gm. Proposed here is a rather pedantic implementation of a combined function, reduced noise, amplifier. It uses paralleled input JFETs as well as cross coupling of these parts to the Gm buffers in an effort to reduce the common mode noise influence for differential sensing. This implementation uses, as usual, the front end as a Gm stage to feed into a differential transimpedance amp. Not as usual, a pair of bipolar current steered Gm amps, between, are cross coupled to drains of JFET pairs. The JFET pairs are mirrored side to side so that common mode noise from each side is split between the Gm amp pairs feeding the Differential final. So noise is reduced in the first order by 1/√N and then by common mode mixing of each side through the Gm buffers. Using the LSK389s, noise is <<1nV/√Hz @ 100Hz. Note that the input differential quad groups are symmetrically mirrored using dual JFETs, half on each side. Gain is then represented by the dual quads’ Gm and current mirrored into the final transimpedance amp. This configuration is designed for 25mVRMS AC input, Gain of 100. Gain and input voltage can be rearranged by input source degeneration and/or transimpedance resistor change. It may seem a bit complicated at first so go back and look at the block diagram to ease that feeling. Your thoughts here are always valuable so, have at it. Fig 1) Block diagram of the concept Fig 2) Full Blown mirrored interstage Gm amps Fig 3) Trimmed down (simplified) Gm mirror stage Fig 4) Boned out to a minimum W/O Gm crossover Fig 5) The minimum minimum W/O Gm crossover As Usual ...... Kirkwood Rough” Kirkwood’s design illustrates how the LSK389 can be used beyond conventional differential amplifier configurations. By combining parallel devices with a symmetrical, cross-coupled architecture, it explores another path toward exceptionally low-noise performance. Interested in designing with the LSK389? Explore the product specifications or contact Linear Systems to discuss your low-noise application.

Last week, we looked at IDSS—the drain current a JFET conducts when VGS = 0 V under specified conditions. This week, we're looking at the other end of the JFET's transfer characteristic: VGS(off), or gate-to-source cutoff voltage. If IDSS helps tell us where the JFET starts at zero gate bias, VGS(off) helps define the point at which the channel is essentially turned off. Understanding both gives engineers a much better picture of how a JFET responds to gate voltage—and how to establish the right operating point for a circuit. What Is VGS(off)? A JFET is a normally-on device. For an N-channel JFET, when the Gate and Source are at the same potential: VGS = 0 V the device conducts drain current. As the Gate becomes increasingly negative relative to the Source, the depletion region expands into the channel and reduces the available path for current. Drain current decreases as this reverse gate-to-source voltage increases. Eventually, the channel reaches the cutoff condition specified by the manufacturer. The gate-to-source voltage associated with that condition is VGS(off). Put simply: VGS(off) tells you approximately how much gate-to-source voltage is required to reduce the JFET's drain current to its specified cutoff level. Why Is VGS(off) Negative for an N-Channel JFET? This is an important distinction when first learning how JFETs operate. An N-channel JFET is already conducting at VGS = 0 V. To reduce that current, the Gate must become negative relative to the Source. That reverse bias expands the depletion region and progressively narrows the conductive channel. So, for an N-channel JFET, VGS(off) is specified as a negative gate-to-source voltage. For a P-channel JFET, the polarities are reversed. VGS(off) and IDSS: Two Ends of the Picture This is where last week's discussion of IDSS connects directly to VGS(off). At one end: VGS = 0 V → ID is approximately IDSS As reverse gate bias increases: VGS becomes more negative → ID decreases And near the other end: VGS approaches VGS(off) → ID approaches the specified cutoff current Together, IDSS and VGS(off) help describe the JFET's transfer behavior. But the useful operating point for an analog circuit is generally somewhere between those conditions. Why Does VGS(off) Matter? VGS(off) gives engineers important information about the gate-voltage range over which the device operates. It can affect: Bias-point selection Source-resistor selection Available signal swing Operating current Circuit headroom Device-to-device variation Overall circuit behavior Just as with IDSS, however, VGS(off) shouldn't be evaluated by itself. A device with a particular cutoff-voltage range isn't automatically better or worse than one with a different range. The important question is whether its characteristics are appropriate for the circuit's intended operating conditions. VGS(off) Is Not Your Operating VGS This distinction is especially important. VGS(off) is a cutoff specification—not necessarily the gate-to-source voltage at which you will operate the JFET. In an amplifier or other linear analog circuit, the JFET is typically biased so that it conducts a desired drain current well before reaching cutoff. The actual operating VGS depends on the desired drain current and the individual device characteristics. So when reading a datasheet, don't interpret VGS(off) as a recommended bias voltage. Instead, think of it as one of the parameters that helps define the device's overall transfer characteristic. Why Is VGS(off) Specified as a Range? Like IDSS, VGS(off) can vary from device to device because of normal semiconductor manufacturing variation. That's why datasheets typically specify a range rather than one exact value. This matters when designing bias networks. A circuit designed around only a typical VGS(off) value may behave differently as individual devices vary within their specified limits. Good analog design accounts for the specified range and establishes an operating point that remains appropriate across expected device variation. How Does It Relate to the Transfer Curve? The JFET transfer characteristic shows how drain current changes as VGS changes. At VGS = 0 V, drain current is near IDSS. As VGS moves toward VGS(off), drain current progressively decreases toward the specified cutoff level. Looking at the transfer curve can therefore tell an engineer much more than simply reading the VGS(off) number from the electrical-characteristics table. It helps visualize where the intended operating point falls between maximum zero-bias conduction and cutoff. What Should You Look for on the Datasheet? When evaluating VGS(off), consider: The specified minimum and maximum values The drain current used to define cutoff The VDS test condition Whether you're evaluating an N-channel or P-channel device The device's IDSS range Your intended drain current The transfer characteristics How device variation could affect your bias point And, as we've emphasized throughout this series, always pay attention to the test conditions associated with a specification. The number alone doesn't tell the entire story. Engineering Takeaway VGS(off) helps define the gate-to-source voltage at which a JFET reaches its specified cutoff condition. For an N-channel JFET: VGS = 0 V → maximum zero-bias conduction near IDSS Increasing negative VGS → decreasing drain current VGS approaching VGS(off) → drain current approaching cutoff But VGS(off) isn't normally the voltage at which you operate the JFET. Instead, it helps define the device's transfer behavior and gives engineers another important piece of information for selecting and properly biasing the device. IDSS tells you about the JFET at zero gate bias. VGS(off) helps define the other end of the transfer characteristic. Understanding what happens between those points is where the real design work begins. Interested in FREE samples of Linear Systems JFETs? Contact us to discuss your application and request samples. Linear Systems Learning Series: Designed for Precision. Built for Performance. #LinearSystems #LearningSeries #JFET #VGSoff #AnalogDesign #PrecisionAnalog #LowNoise #Semiconductors #ElectronicsEngineering #AnalogElectronics

This week’s Design Spotlight takes us into a sonar application proposed for multi-channel aquatic imaging. The design uses a dual matched JFET front end to meet the sensor’s differential loading requirements while providing the low-noise, high-speed performance needed for downstream A/D conversion. “Just another JFET circuit that was composed and built for a Sonar application, proposed to be used in multiple for aquatic imaging. One of the requirements was a loading impedance of 100 megohms for the sensor and an overall bandwidth of 5MHz. A couple of parameters to start with that aren’t typically specified together. This front-end using a dual matched JFET worked to satisfy the differential load requirement of this Piezo sensor. The input stage is sourced by a JFET current source and the input gates are biased at -6V. Both Drains would be feeding into ground referenced resistors so would need enough voltage offset to the gates to remain linear. From there a typical JFET differential current to voltage amplifier done in discrete parts is used for low noise gain. Only an 18pF capacitor was needed for amplifier compensation to eliminate the minor overshoot. Using a linear low gain discrete op-amp allows for high-speed performance with acute transient response. Compensation of an integrated op-amp is typically a compromise between speed and overshoot. Not much unusual here except that the amplifier cluster needed to be transient / EMI rugged and closely repeatable over a relatively wide temperature range. In addition, these were coated in a Parylene deposition to lock out moisture while maintaining a low dielectric influence on the circuit. Each single ended output was then matrixed to an A-D conversion bank and processed by FPGAs to resolve imaging with a little math. This, like many circuits was done by necessity and on the run. As usual ………… Kirkwood Rough” Designing a high-impedance, low-noise front end for piezo, sonar, hydrophone, or other demanding sensor applications? Explore Linear Systems ultra-low-noise JFETs, or contact us to discuss your application and request FREE engineering samples. hashtag#LinearSystems hashtag#JFET hashtag#JFETDesign hashtag#AnalogDesign hashtag#Sonar hashtag#PiezoSensor hashtag#AquaticImaging hashtag#LowNoise hashtag#SensorDesign hashtag#AnalogElectronics hashtag#Semiconductors