UNDERSTANDING JFET BREAKDOWN RATINGS: WHAT BVGSS AND ABSOLUTE MAXIMUM RATINGS REALLY MEAN
A JFET datasheet may list a high gate-to-source breakdown voltage—but that does not mean the device should normally operate at that voltage.
Breakdown ratings, electrical specifications and absolute maximum ratings describe different boundaries. Confusing them can expose a JFET to excessive junction current, transient stress or long-term reliability problems.
Understanding those distinctions is especially important in high-impedance circuits, where protection must be added without introducing excessive leakage, capacitance or noise.
WHAT DOES BVGSS MEAN?
BVGSS is the gate-to-source breakdown voltage measured under specified test conditions, normally with the drain and source at the same potential.
A JFET’s gate forms a PN junction with its channel. During normal operation, that junction is reverse-biased:
In an N-channel JFET, the gate is normally negative relative to the source.
In a P-channel JFET, the polarities are reversed.
As the reverse voltage across the gate junction increases, it eventually reaches breakdown. At that point, gate current rises sharply.
BVGSS identifies the voltage at which a specified test current flows. It is not a recommended operating voltage.
For an N-channel JFET, the datasheet may show BVGSS as a negative voltage because of the applied polarity. It is also common to discuss the rating by its absolute magnitude. Engineers should always check the sign convention and test conditions in the applicable datasheet.
BVGSS IS NOT VGS(OFF)
BVGSS and VGS(OFF) describe completely different device conditions.
VGS(OFF) is the gate-to-source voltage required to reduce drain current to a specified low value. It is a normal electrical characteristic used when evaluating biasing and cutoff behavior.
BVGSS describes reverse breakdown of the gate junction.
In simplified terms:
VGS(OFF) helps describe how the JFET is controlled.
BVGSS identifies the gate-junction breakdown boundary.
Although both specifications involve gate-to-source voltage, they must not be treated as interchangeable.
BREAKDOWN VOLTAGE VERSUS MAXIMUM VOLTAGE
A datasheet may show gate-to-source voltage in more than one section.
The electrical-characteristics table may list BVGSS as a minimum breakdown voltage under a specific test condition. This means the device should not enter breakdown before reaching the stated voltage magnitude under that test.
The absolute-maximum table may separately list a maximum VGSS. This is a limiting value that the circuit must not exceed.
These specifications serve different purposes:
BVGSS describes a measured device characteristic.
Maximum VGSS defines a stress limit.
Neither value establishes a recommended continuous operating voltage.
Neither guarantees acceptable noise, leakage or reliability when operating close to breakdown.
A reliable design normally maintains appropriate margin below every applicable maximum rating.
WHY DRAIN VOLTAGE ALSO MATTERS
A JFET contains both gate-to-source and gate-to-drain junctions.
For an N-channel JFET operating with its drain positive relative to its source, the gate-to-drain junction may experience substantial reverse voltage even when the gate-to-source voltage appears safe.
The terminal voltages are related by:
VGD = VGS - VDS
This means that checking VGS alone is not enough.
If the gate and source are near the same potential while the drain rises positively, the gate-to-drain junction sees nearly the full drain voltage in reverse bias.
Depending on the datasheet, the applicable limits may include:
VGSS: Maximum gate-to-source voltage
VGDS: Maximum gate-to-drain voltage
BVGSS: Gate-to-source breakdown voltage under specified conditions
BVGDS: Gate-to-drain breakdown voltage under specified conditions
VDS or BVDSS: A separately stated drain-to-source voltage or breakdown rating
Not every JFET datasheet uses the same combination of ratings. The circuit must be checked against the exact limits provided for the selected device.
ABSOLUTE MAXIMUM DOES NOT MEAN NORMAL OPERATION
Absolute maximum ratings are limiting values—not recommended operating conditions.
Reaching an absolute maximum value does not guarantee that the device will continue to meet its electrical specifications. Exceeding it may damage the device immediately, while repeated or extended operation near the boundary may affect long-term reliability.
Absolute maximum tables may include limits for:
Gate-to-source voltage
Gate-to-drain voltage
Forward gate current
Drain current
Power dissipation
Junction temperature
Storage temperature
Package or lead temperature
These limits also interact.
A device operating below its maximum voltage can still be overstressed by excessive current, power dissipation or junction temperature. Likewise, a brief voltage transient may exceed a junction rating even when the circuit’s steady-state voltage is well within limits.
Unless the datasheet specifically says otherwise, engineers should not assume that multiple absolute maximum ratings can be reached simultaneously.
OPERATING SPECIFICATIONS VERSUS SURVIVAL LIMITS
Electrical characteristics describe how a device performs under stated test conditions.
These specifications may include:
IDSS
VGS(OFF)
Transconductance
Output conductance
Gate leakage
Voltage-noise density
Capacitance
Matching characteristics
Absolute maximum ratings define boundaries beyond which the device’s serviceability may be impaired.
A useful way to interpret the datasheet is:
Electrical specifications describe performance.
Normal circuit conditions establish intended operation.
Absolute maximum ratings establish stress boundaries.
Breakdown measurements characterize a junction boundary under a specific test.
A circuit should be designed around the required operating performance—not around the assumption that the device can continuously tolerate its absolute maximum ratings.
WHY TRANSIENTS ARE EASY TO MISS
A circuit may remain comfortably within its limits during steady-state operation while exceeding them during a brief event.
Possible sources of transient stress include:
Power-supply startup and shutdown
Hot-plugging connectors or circuit boards
Charged input cables and sensors
Electrostatic discharge
Inductive switching
Supply overshoot
Input signals applied before the bias supplies stabilize
Amplifier overload or clipping
Large common-mode steps
Capacitive coupling through the gate-to-drain capacitance
Test equipment connected to an unpowered circuit
These events may last only microseconds, but semiconductor junctions can respond much faster than a handheld meter or slow oscilloscope display.
The correct question is not only:
“What is the normal operating voltage?”
Engineers should also ask:
“What is the worst instantaneous voltage between every pair of terminals during startup, shutdown, overload and external connection events?”
WHAT HAPPENS WHEN THE GATE JUNCTION BREAKS DOWN?
When the reverse-biased gate junction enters breakdown, gate current can increase rapidly.
Whether the device is damaged depends on factors including:
Current magnitude
Pulse duration
Repetition rate
Junction temperature
Source impedance
Energy available from the circuit
Device construction
Whether breakdown operation is explicitly permitted by the manufacturer
A junction may survive the controlled, current-limited test used to verify its breakdown specification. That does not mean uncontrolled or repetitive breakdown is safe.
Possible consequences of excessive stress include:
Increased gate leakage
Changed electrical characteristics
Higher noise
Reduced input impedance
Degraded matching in a dual device
Latent reliability damage
Immediate junction failure
In a precision circuit, a device does not need to fail completely to become unsuitable. A small increase in leakage or noise may be enough to compromise system performance.
FORWARD GATE CURRENT MATTERS TOO
Reverse breakdown is not the only gate-junction concern.
If the gate becomes forward-biased relative to the source or drain, the gate junction begins to conduct like a diode. The resulting current must remain within the datasheet’s forward-gate-current limit.
Forward bias can occur during:
Input overload
Incorrect power sequencing
AC signals larger than the available bias margin
Fault conditions
External signals applied while the circuit is unpowered
Once the gate junction conducts, the input no longer behaves as an extremely high-impedance node. Signal distortion, bias shifts and excessive current can result.
PROTECTING A JFET WITHOUT DEGRADING PERFORMANCE
Protection is particularly challenging in low-noise and high-impedance circuits because the protection components can affect the signal.
Possible protection methods include:
A series gate resistor to limit fault current
Low-leakage clamp diodes
Carefully selected transient suppressors
Controlled supply and input sequencing
Drain-voltage clamping
Current-limited bias supplies
Protection from charged cables and sensors
Short, controlled PCB traces
Proper grounding and shielding
ESD-safe handling and assembly procedures
Each method involves tradeoffs.
A series resistor produces thermal noise and can interact with input capacitance to limit bandwidth. A protection diode may add leakage and capacitance. A transient suppressor that works well on a power input may be unsuitable for a picoampere-level sensor node.
The protection network should be evaluated for:
Leakage over temperature
Capacitance
Noise
Clamp voltage
Response time
Maximum current
Energy capability
Effect on bandwidth and stability
Behavior when the circuit is powered off
Protection should be selected for the complete application—not added according to a generic rule.
TEMPERATURE AND POWER STILL APPLY
Voltage ratings cannot be evaluated separately from temperature and power dissipation.
The JFET’s junction temperature depends on:
Ambient temperature
Drain current
Drain-to-source voltage
Package thermal resistance
PCB layout
Airflow
Nearby heat sources
Transient and continuous power
Approximate device power dissipation during normal operation can be calculated as:
PD = VDS x ID
The result must remain within the device’s power and junction-temperature limits with suitable design margin.
Package options may also have different thermal characteristics. A voltage and current combination that is acceptable in one package or board layout should not automatically be assumed acceptable in another.
A PRACTICAL BREAKDOWN-RATING CHECKLIST
Before finalizing a JFET circuit, ask:
What are the gate-to-source and gate-to-drain voltage limits?
Is a separate drain-to-source limit specified?
What polarity applies to each rating?
Under what conditions was BVGSS measured?
What is the maximum forward gate current?
What voltage appears between every terminal pair during normal operation?
What happens during startup and shutdown?
Can an input remain connected while the circuit is unpowered?
Could a charged cable, sensor or capacitor drive the gate beyond its limits?
Are inductive or supply-switching transients possible?
Does the protection network add unacceptable leakage, capacitance or noise?
Are power dissipation and junction temperature within their limits?
Has adequate design margin been maintained?
Does the circuit remain safe across component tolerances and temperature?
Are the selected values operating specifications or absolute maximum ratings?
LINEAR SYSTEMS JFET RATINGS
Linear Systems offers JFETs for low-noise, high-impedance and precision analog applications, including the LSK170, LSK389, LSK489, LSK189, LSBF862 and complementary P-channel devices.
The applicable voltage, current, power and temperature ratings vary by product. Power and thermal limitations may also depend on the package. Engineers should use the current datasheet for the exact device and package being evaluated.
For example, the LSK170 datasheet separately identifies:
Gate-to-source breakdown voltage as an electrical characteristic
Maximum gate-to-source voltage
Maximum gate-to-drain voltage
Maximum forward gate current
Continuous power dissipation
Operating-junction and storage-temperature ranges
That separation illustrates why a single breakdown-voltage number cannot define the complete operating boundary.
ENGINEERING TAKEAWAY
A JFET’s breakdown rating is not its recommended operating voltage.
BVGSS identifies the reverse gate-junction breakdown point under specified test conditions. Absolute maximum ratings establish stress boundaries beyond which the device’s serviceability may be impaired. Neither should be treated as a normal design target.
Reliable JFET design requires engineers to consider:
Gate-to-source voltage
Gate-to-drain voltage
Drain-to-source voltage
Forward gate current
Transient conditions
Power dissipation
Junction temperature
Protection-component leakage and capacitance
Adequate operating margin
The circuit must remain within its limits not only after it settles, but also during startup, shutdown, overload and every realistic external fault.
Understanding these boundaries helps protect the JFET while preserving the low leakage, low noise and high input impedance that made it the right device for the application.
For FREE samples of Linear Systems’ JFETs click the link below:
