TEMPERATURE COMPENSATED JFET CAPACITIVE ACCELEROMETER AMPLIFIER

“An accelerometer is typically a capacitive transducer and varies Cacc with acceleration rate. A common problem with resident current fed accelerometer preamps is excessive DC offset drift when used up to 100 C. The object here was to keep the output bias voltage within +/- 25% of the 10-volt setting. The LS5906 Low bias Dual JFET addresses this temperature dependency by a unique internal DIE coupling in its construction. In this circuit, compensation of J1’s gate current over temperature happens by an inter-DIE Gate/Substrate coupling current where J2’s gate/drain junction is negative relative to J1’s gate where J1’s Gate current relates to the positive end of the drain channel. The JFETs close proximity on a common DIE assures uniform doping distribution and results in equal junction characteristics. By setting both FETs to have approximately the same Vgd, Gate currents are nearly the same and with opposed junctions, will null out an operating bias current of the active FET over a wide range of temperature. Normal doubling of leakage in silicon every 7 C is then reduced to less than a few percent. Though there is a lot of latitude to modify the dual JFETs Vgd balance for even better performance, this circuit satisfied an immediate requirement and was refined no further. Tests were successful up to 100 C.  However, the principle of balanced opposing gate currents for temperature compensation here should be noted for other possible single ended designs where gate current temperature drift is a critical issue.” - Kirkwood Rough

What are your thoughts on using balanced opposing JFET gate currents to mitigate temperature drift?

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