LS26VNS

The LS26VNS N-Channel Single JFET voltage controlled resistor has a drain-source resistance that is controlled by a DC bias voltage (VGS) applied to a high impedance gate terminal. Minimum RDS of 14 Ω occurs when VGS = -1.0V. As VGS approaches the pinch-off voltage of -6.0V RDS rapidly increases to the maximum value or RDS = 38 Ω. For the P-Channel version, please see our LS26VPS. Both the N and P-channel parts are made from the same die geometry, making them complimentary.