# JFET Circuit Design Book

Linear Systems

Jul 8, 2024

JFET Design Basics: Basic Amplifier Configurations, Common Source Small Signal AC Equations, Common Drain and Common Gate Small Signal Equations, Bias Techniques

**JFET Design Basics**

##### BasicÂ AmplifierÂ Configurations

Understanding analog electronic system design requires that one understands the basic amplifier blocks. The three basic JFET amplifier configurations are the common source, the source follower (or common drain), and the common gate. The simplified equations shown are for low-frequency operation. As the input frequency increases, the input capacitance of the JFET must be considered.

##### CommonÂ Source SmallÂ SignalÂ AcÂ Equations

Taking a closer look at just the common source configuration, the table below illustrates how voltage gain, input impedance, and output impedance vary for three topology variations: Common Source, RS bypassed, simple RG; Common Source, No RS bypass, Simple RG; and Common Source, RS bypassed, RG Voltage divider. These methods, the coupling capacitor values, and bypass capacitor values will affect the small signal and low-frequency gain. The equations include the effects of the drain-to-source resistance, rd. This is the dynamic resistance at the Q-point at which the amplifier is biased. For amplifiers operated in the saturation region, this is the inverse of the output conductance at the Q-point, which can be found on the JFET datasheet or inferred from its associated IV characterization curve. See the subsequent section on Bias Techniques for a closer look at the Q-point.

##### CommonÂ DrainÂ andÂ CommonÂ GateÂ SmallÂ SignalÂ Equations

TheÂ tableÂ belowÂ indicatesÂ theÂ voltageÂ gain,Â inputÂ impedance andÂ outputÂ impedance forÂ theÂ commonÂ gateÂ and commonÂ drainÂ (sourceÂ followers)Â topologiesÂ whenÂ theÂ drain-to-sourceÂ resistanceÂ isÂ included.

##### BiasÂ Techniques

Biasing is an important consideration, since a JFETâ€™s operating characteristics can vary significantly from part to part. Specifically, Vgs(off) and IDSS can vary substantially and affect the performance of the amplifier, switch, current source, or whatever other application the JFET is used in. JFET biasing schemes are often selected to ensure that variations in JFET parameters will not substantially affect the performance of the circuit.

There are numerous ways to establish a DC bias point for a JFET. Some analytic methods result in better Q-point stability when compared to other methods. Q-point instability results from JFET process variations. The simplest biasing methods are the self-biased, source-biased, and the current-biased configurations. There is also a voltage divider bias configuration, seen previously in the Basic Amplifier Configurations chart. The current-biased configuration, which uses a JFET current source (see the current source section), is noted for a more stable Q-point and lower distortion. The reason is that the current source fixes the drain-to-source current which keeps the Q-point from changing as a result of AC signal input changes â€“ i.e., it has better Q-point stability.

For a more detailed analysis on these circuit configurations and biasing techniques, refer to the Teledyne Applications Note, "JunctionÂ FETsÂ Theory and Applications".